The invention relates to a circuit layout for measuring ion concentrations in solutions using ion-sensitive field effect transistors (ISFETs).
There is an increasing need for circuit layouts for determining ion concentrations and, in particular in the biomedical field, circuit layouts which can be integrated into a very small space are required, for example, for performing measurements on blood or urine.
The function of chemical sensors, on the basis of ion-sensitive field effect transistors, is based on the change to the threshold voltage of an ISFET as a function of the ion concentration in liquid electrolytes. The function of a circuit layout for determining the ion concentration with ISFETs is therefore limited to a threshold voltage measurement. The difficulty encountered is, inter alia, that with real ISFETs the desired sensor signal also has a strong dependence on different ambient influences and is also influenced by threshold voltage drifts caused by age.
A widely used method for determining the ion concentration in solutions is to measure the threshold voltage difference between an ISFET and a reference MOSFET, which operate in a negative feedback differential amplifier configuration. However, with this method it is only possible to compensate the parasitic threshold voltage influences, which are caused by the MOSFET configuration, so that, for example, external influences acting differently on the MOSFET and ISFET lead to erroneous measurements (operating point dependence of the threshold voltage). It is also disadvantageous that the known circuit layout can only operate in a narrow range around the prescribed operating point, so that it is not possible to compensate technological and operation- ally caused parameter fluctuations. Much better results can be obtained if the threshold voltage difference of two ISFETs having different sensitivities is evaluated. The use of ISFETs having different sensitivities presupposes the technical control of differently sensitive layers during the manufacturing process (cf. e.g. Isemi Igarashi et al: Multiple Ion Sensor Array, Sensors and Actuators, B1 (1990), pp.8-11). The measurement of this threshold voltage difference is not possible in the above-described manner in a simple differential amplifier, because the two ISFETs have a common gate connection in the electrolytic solution.
The subtract amplifier configuration described by A. Sibbald: A Chemical-Sensitive Integrated Circuit: The Operational Transducer, Sensors and Actuators, 7, 1985, pp.23-28 and specifically described on page 27 therein, suffers from the disadvantage that further circuit-caused quantities enter into the measured result and that it is necessary to calculate back from the output signal of the circuit, via the operating point current, to the actual sensor signal. Another disadvantage is that the two FETs are necessarily operated at different operating points, so that ambient influences cannot be compensated with the circuit.
German Patent document DE-A-3 216 791 discloses a circuit layout for measuring the ion concentration using ISFETs with different sensitivities. In this reference, the drain current of the ISFETs is kept constant by readjusting the gate voltage and the necessary voltage change for this is evaluated. However, the proposed circuit layout suffers from the disadvantage that disturbance variables, which can, for example, be caused by the amplifier or by operationally caused or technological tolerances, cannot be compensated. The prerequisite necessary for the error-free function of the circuit layout, i.e., that the difference in the transconductances of the ISFETs must be constant, cannot be ensured in the case of real ISFETs, so that this gives rise to an additional error source.
There is therefore needed a circuit layout with which it is possible to make available the threshold voltage difference of two ISFETs, having either the same or different sensitivities, for the ionic species to be measured in a direct manner independently of technologically caused tolerances, operationally caused parameter fluctuations and ambient influences. The threshold voltage difference should be made available as an analog output voltage, thus making it possible to test ISFETs for identical parameters.
According to the present invention, these needs are met by a circuit configuration formed from two measuring or test amplifiers. In the input stages of each of the measuring amplifiers, two ISFETs and two identical FETs are connected in such a manner so that the output voltage of the first measuring amplifier corresponds to the difference between the mean value of the two ISFET threshold voltages and the FET threshold voltage and the output voltage of the second measuring amplifier corresponds to the difference of the two ISFET threshold voltages of the amplifier. Thus, at the output of the first measuring amplifier there is always the offset voltage of the overall circuit layout. This offset voltage can be time-varied, for example, on the basis of external influences. By connecting the output of the first measuring amplifier to the common reference electrode of the four ISFETs, the operating point of the second measuring amplifier is fixed. Thus, the subtraction in the second measuring amplifier always takes place symmetrically to the operating point fixed by the first measuring amplifier. The output voltage of the second measuring amplifier represents the sensor signal, i.e. the threshold voltage difference between two ISFETs, and for an error-free measurement the ISFETs and FETs of the first measuring amplifier must be identical to those of the second amplifier. The FETs used in this circuit can, for example, be MOSFETs.
With the circuit layout according to the present invention, it is possible to directly make available the threshold voltage difference of two ISFETs, i.e., for example, without any additional computing expenditure, as an analog output voltage. As the operating point of the second measuring amplifier is determined by the output of the first amplifier, subtraction automatically takes place symmetrically to the set operating point in all cases. Therefore, the measurement by the circuit layout according to the present invention is advantageously independent of technologically caused tolerances of components, age-caused threshold voltage drifts, or fluctuations to operating parameters, such as temperature or operating voltage changes. The circuit layout according to the invention can also, for example, in the form of a CMOS circuit, be integrated into a modified standard process together with the ISFET sensors on a single chip, so that consequently measurements are possible in a highly confined space.
In a particularly advantageous embodiment of the circuit layout according to the present invention, two ISFETs having different sensitivities are used in the input stages of each of the two measuring amplifiers for the ionic species to be measured. This circuit layout makes it possible to link the advantages when determining the ion concentration with differently sensitive ISFETs with the aforementioned advantages of the circuit layout according to the invention.
A further advantageous embodiment of the circuit layout according to the present invention, in which there are two identically sensitive ISFETs in the input stages of the two measuring amplifiers, makes it possible to determine local concentration differences in an electrolytic solution (e.g. in a capillary).
During the measurement, the two ISFETs of the second measuring amplifier are separately positioned at two different locations in the solution to be measured. The two ISFETs of the first measuring amplifier, for example, together with the reference electrode, can be centrally positioned between the positions of the two ISFETs of the second measuring amplifier. If the ion concentrations at the two locations of the ISFETs of the second measuring amplifier are identical, then no voltage (U.noteq.OV) is applied to the output of the circuit layout according to the invention. A corresponding output signal is obtained when concentration differences occur.
In a further preferred embodiment of the circuit layout according to the invention, the first measuring amplifier includes a known operational amplifier circuit, in which the input differential stage is replaced by a circuit layout of two differential amplifier stages. These differential amplifier stages in each case include a power source, a FET and an ISFET, which are connected in the following manner. The source connections of the FETs and ISFETs are in each case connected to the power source, the drain connections of the ISFETs to a load element common to both differential amplifiers, the drain connections of the FETs to a second load element common to both differential amplifiers and the gate connections of the two FETs to the reference potential, i.e., ground.
The connections of the load elements to the drain connections of the ISFETs and FETs are incorporated into the operational amplifier circuit so that emanating from the drain connections of the FETs and up to the output of the amplifier there is a negative sign of the gain and emanating from the drain connections of the ISFETs and extending up to the output of the amplifier there is a positive sign of the gain.
In a still further preferred embodiment of the circuit layout according to the invention, the second measuring amplifier includes a known operational amplifier circuit, in which the input differential stage is replaced by a circuit layout having two differential amplifier stages. These differential amplifier stages in each case comprise a power source, an FET and an ISFET, which are connected in the following manner. The source connections of the FETs and ISFETs are in each case connected to the power source, the drain connections of the ISFET of the first differential amplifier and the FET of the second differential amplifier to a common load element, and the drain connections of the FET of the first differential amplifier and the ISFET of the second differential amplifier to a second common load element. The gate connection of the first FET is connected to the reference potential, i.e., ground, and the gate connection of the second FET to the output of the amplifier.
The connections of the load elements to the drain connections of the ISFETs and FETs are incorporated into the operational amplifier circuit so that, emanating from a connection point of the first load element to the drain connections and extending to the amplifier output, there is a negative gain sign, and starting from the connecting point of the second load element to the drain connections and extending to the amplifier output, there is a positive gain sign.
According to a further embodiment, of the circuit layout according to the invention, use is made of FETs and ISFETs with the same layout. The four identical FETs are dimensioned in such a way that they have roughly the same transconductance as the four ISFETs. The four identical currents of the power sources are set so that the operating points of the ISFETs and FETs are well in the active range.
A preferred embodiment of the invention is obtained if MOSFETs are used as the field effect transistors (FETs).
According to a further embodiment of the circuit layout according to the invention, the currents of the power sources are made available by a bank of MOSFETs.
In another preferred embodiment of the circuit layout according to the invention, the reference electrode is made from an electrically good conducting material, which has a chemical resistance to the electrolytic solution, such as, for example, gold or platinum.
In a further embodiment according to the invention, the inventive circuit layout is in the form of a CMOS circuit and is integrated in a modified standard process together with the ISFETs on a single chip, so that the circuit layout permits measuring in a very confined space.
The circuit layout according to the present invention can be used for testing ISFETs. Whereas when using identical ISFETs at the same point in an electrolytic solution the threshold voltage difference is zero, differences of the ISFETs, which are, for example, due to technological parameter fluctuations during the manufacturing process, can be detected by a voltage (U.noteq.OV) applied to the output of the circuit layout. It is therefore possible to test the ISFETs for identical parameters.